Petrify: Method and Tool for Synthesis of Asynchronous Controllers and Interfaces
by Alex Yakovlev, University of Newcastle upon Tyne

Abstract


In this tutorial the audience will be familiarised with the synthesis of asynchronous control circuits from Signal Transition Graphs (STGs). Conceptually, STGs are similiar to sets of Timing Diagrams and hence are simple in use. Mathematically, they are interpreted Petri nets and therefore have a clear formal meaning, used in synthesis algorithms.

The tutorial will introduce tool Petrify, which can automatically synthesize a speed-independent logic implementation for an STG specification. The audience will have a chance to build a number of simple interface circuits using Petrify. More information about Petrify (including how to download) can be found on http://www.lsi.upc.es/~jordic/petrify/petrify.html

Verifying, Designing, and Testing Asynchronous Circuits in FIREMAPS
by Radu Negulescu, McGill University

Abstract


FIREMAPS is a tool for structured verification, design, and test of asynchronous circuits based on the process spaces theory. Using state graph specifications of small asynchronous circuits, the tutorial will demonstrate the following operations supported by FIREMAPS:

- verify safety and deadlock-freedom properties

- model gate-level, switch-level, relative timing, and clocked circuits

- determine test vectors and test patterns

- design supervisory control

- verify compliance to several handshake protocols

- recast (reversibly convert) from one protocol to another

Persia: an Asynchronous Synthesis Tool Based on Alain Martin's Method
by Arash Saifhashemi, Mohsen Naderi, Hossein Pedram, Tehran Polytechnic

Abstract


Persia is a synthesis tool for synthesizing asynchronous circuits based on Martin's synthesis method. It helps the designer to get rid of those time-consuming jobs that are easy to be automated such as implementing handshaking protocols, generating state tables, reporting if a state variable is needed, generating the production rules, finding if there is any non-empty window, reporting isochronic forks, operator reduction, making production rules become CMOS mappable, generating the CMOS net list, etc.

All input and output files (except for the report files) are in standard Verilog language. Therefore, all intermediate files can be simulated on a regular Verilog simulator, and a single test bench can be used for testing the circuit at all levels.

At the highest level, the behavior of the circuit is described in CHP language. CHP language constructs are modeled in Verilog HDL using PLI (Programming Language Interface) routines and macros. Therefore, a circuit described at this level can be simulated Verilog simulators that support PLI. The lowest level is switch level (CMOS mappable production rules).

The tool consists of several sub-programs that each roughly corresponds to a synthesis level of Martin's method, so the designer can feed a circuit, which can be at any level of the synthesis, into the tool independently.

This tool has little thing to do with the stages that would be rather complicated to be automated such as process decomposition, variable insertion, reshuffling, slack matching, etc. Therefore, such steps still should be done manually by the designer. However, as our future work, we would make the tool generate some guidelines for the designers to simplify these steps.

Weaver: a Synthesis Flow (beta version) for Fine-Grain Pipelining Based on a Commercial Synchronous Engine
by Alexandre Smirnov and Alexander Taubin, Boston University

Abstract


We will talk about an automatic flow for the design of asynchronous circuits providing reasonably high performance due to dual-rail, fine-grain integrated pipelines and low adoption costs (from synchronous to asynchronous flow) because it closely mimics the conventional synchronous HDL methodology and relies on commercial and/or standard design tools.

The approach behind the tool combines a template based fine-grain pipelining with logic synthesis and optimization capabilities of the Synopsis CAD tool. The range of supported language constructs in the input HDL specification is provided by the Synopsis Design Compiler. Its usual design flow is, however, interrupted by expanding conventional data lines to dual-rail encoded (and pipelined) and substituting conventional gates by asynchronous ones. The modified netlist is fed back to the Design Compiler and technology mapper. This way all the design stages remain the same. HDL description can be provided at all design stages and simulated with conventional simulation tools and the output is produced in the conventional form. The flow is in its early development stage (beta version) but is already capable to deliver fine-grain pipelined asynchronous circuits.

MV-SIS
by Yunjian Jiang, UC Berkeley

Abstract


A program called MV-SIS has been developed which optimizes multi-level, multi-valued networks (MVnetworks). We describe what such a network is and the capabilities contained in MV-SIS. MV-SIS is modeled after SIS, which synthesizes binary multi-level networks, but the logic network of MVSIS is such that all variables can be multi-valued (including binary valued) each with its own range. Included in MV-SIS are almost all the technology-independent transformations of SIS for combinational and sequential logic synthesis as well as transformations specific to multi-valued nodes such as merge, pair-decode, encode. MVSIS can read and write BLIF-MV and BLIF files which describe MV-networks and binary networks, respectively. A new version of MV-SIS has just been created which is much faster (even much faster than SIS), and will be demonstrated at the meeting. Technology mapping into PLA-like structures appropriate for QDI asynchronous synthesis will be discussed.