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At the ASYNC 2001 conference, Sun Microsystems Laboratories described
FLEETzero,
a prototype chip with raw speed roughly
twice that of today's chips. Where today's chips use "synchronous"
circuits with a global clock to manage activity, the new, faster
FLEETzero chip uses radical new circuits with low-power, asynchronous
logic elements that produce timing signals only where and when needed.
The Asynchronous Design Group at Sun Microsystems Laboratories is onto ideas that may shift the dominant paradigm for integrated circuit design. "We have three guiding design principles," Ivan Sutherland likes to say of his team's work at Sun Microsystems Laboratories, "speed, Speed, and SPEED." Ivan, Sun Microsystems Fellow and Vice President, heads the Asynchronous Design Group. Its members include Jo Ebergen, Bill Coates, Ian Jones, Jon Lexau, Scott Fairbanks, Jon Gainsley, Wes Clark, Mark Greenstreet, and David Harris. Together, they recently developed a proof-of-concept prototype, the FLEETzero chip. The asynchronous FLEETzero chip is the culmination of 10 years of research and more than 3 dozen earlier experimental chips. With the FLEETzero chip, the team not only has built a quicker data pipline, but also developed two radical new approaches to chip design - one based on new circuits and one based on novel architecture. Both approaches offer circuit and microprocessor designers freedom from the tyranny of system clocks. The Circuit Problem: Energy Sinks That Run Hot Virtually all of today's digital circuits quantize time with a global clock. The global clock pulses millions of times each second to orchestrate chip operations. The clock signals go everywhere on the chip to set the latches and work the gates that keep data moving. But because wires are slow, the clock signals are subject to delay as they travel inside each chip and from chip to chip. With wires getting thinner and data traffic heavier, synchronous circuit designers must devote a growing proportion of chip resources to the clock drivers that manage timing. Each part of the chip waits for a clock signal before performing its next operation; this slows down the actual data processing, keeping performance well below the potential speed of the individual transistors. Today, for example, individual logic transistors -- the on-off switches that move data -- can run as much as 20 times faster than the system clocks that regulate them. Moreover, the resources that support the global clock consume a large part of the total power in a high-performance microprocessor because the system clock keeps on ticking whether needed or not. The combination of increasing wire delays and increasing power consumption affects both the physical and performance limits of todays synchronous systems. The Architecture Problem: Operations not Communication Today's synchronous circuits are designed in terms of operations such as addition, division and I/O. According to Ivan and his colleagues, this operations-centric view made sense in the simpler, older world of vacuum tubes and transistors of the 1940s and 50s. "Early computers emerged in an era when logic cost far more than communication, not only in financial terms, but also in terms of delay, power consumption and volume", so naturally people thought in terms of operations as basic to the design process. Today, with each circuit sporting many millions of transistors, the cost of logic has plunged, leaving communications as the high cost task. Yet operation-centric design, based on a high cost of logic, remains dominant. Today, "The task of getting two numbers to an adder takes more chip area, consumes more energy, and takes longer than doing the addition," noted the team in a recent paper. The Asynchronous Solution In a series of four papers delivered this spring, the Asynchronous Design Group described a new approach to designing integrated circuits. The new approach embodies the asynchronous principle that allows the logic itself to manage the time and resources required to move data. This simplifies design by eliminating the circuitry required to manipulate a system clock. The team's approach is based on a very simple form of control logic with uniform gate delay. The uniform delay is accomplished by applying what the team calls the theory of Logical Effort. Logical Effort theory tells how to make transistors only as wide as they need to be to achieve the desired speed. The theory is described comprehensively in Logical Effort: Designing Fast CMOS Circuits, by Ivan Sutherland, Bob Sproull and David Harris.
Two of the four papers directly address issues of circuit and architecture design. The first paper, "GasP: A Minimal FIFO (First In-First Out) Control" by Ivan Sutherland and Sun Labs researcher Scott Fairbanks describes a set of asynchronous building blocks. These self-timed circuit primitives permit designers to construct data processing networks that branch and merge, forming connections that are to data what freeway interchanges are to traffic. Such asynchronous circuits offer high speed because they are composed of few transistors which coordinate the actions of adjacent building blocks.
The second paper, "FLEETzero: An Asynchronous Switch Fabric Chip Experiment" by Bill Coates, Jon Lexau, Ian Jones, Scott Fairbanks and Ivan Sutherland, describes a novel computer architecture that replaces today's focus on instructions with a focus on data movement. The FLEETzero chip developed by the team stands as the first embodiment of this novel architecture. In the FLEETzero chip, each processing element, called a "ship", performs its own function at its own pace. Binary code routes data from ship to ship. What happens to the data, addition, multiplication, etc., depends on where it goes. Compilers, similar to those in use today, can convert standard programs into the new binary formats required. The paper envisions development of FLEET-based technology to create larger devices where FLEETs scale up into FLOTILLAs. Two additional papers address the issues of speed and switching control. "Designing Fast Asynchronous Circuits" by Ivan Sutherland and Sun Labs researcher Jon Lexau proposes a new design flow to obtain optimal speeds for asynchronous control circuits by balancing transistor widths to achieve desired delay characteristics. Transistor widths are crucial, because they determine the switching speeds of the logic gates in the control circuit. "Squaring the FIFO in GasP" by Sun Labs researcher and Sr. Staff Engineer, Jo Ebergen, shows how asynchronous circuits can be used to control complex switching functions. The paper describes a new set of schematic symbols that graphically represent the actions of asynchronous circuits. As an example, these symbols are used to design an asynchronous high-speed FIFO circuit, a fundamental building block for many systems. The FLEETzero Chip: So How Does It Work? The communication-centric design focus of the FLEETzero chip concentrates on how the data moves through the circuit. The arrival of data triggers the operations. This "lets the programmer specify a sequence of data movements," the team notes, so that "operations become side effects of where the program sends data." Consequently, only the portions of the circuit that are required for computation are actually active. As Ivan puts it, "Our circuits stand still when they're not working. Synchronous circuits keep jogging in place." Asynchronous circuits achieve speed by allowing each gate to set its own pace rather than waiting for the next tick of a system clock, whose pace is set by the slowest part of the chip. Thus asynchronous circuits require far less power, because they do without the biggest energy user, the global clock.
The Future: Islands of Asynchrony
The outlook for asynchronous circuits is bright. Because they are faster and require less power, asynchronous processors are ideally suited for battery-driven notebook computers, personal digital assistants (PDAs), cellular telephones, and many other portable electronic systems that require low-power, low-voltage, high-performance processors. In addition, a processor built using asynchronous circuits solves the pervasive problem of radio interference. Because the different parts of an asynchronous chip run at different speeds, it broadcasts much less interference at any single radio frequency. The Asynchronous Design Group is delivering on its charter to investigate new and disruptive technologies with the potential for near and medium-term integration into Sun Microsystems products. Next steps include adapting the technology to the requirements of Sun product divisions as well as further research on expanding the range of asynchronous circuit types, topologies, and techniques. Although complete computers built on Sun Labs-developed asynchronous technologies may be years away, aspects of it may reach market sooner when embedded as specialized subsystems within larger, predominantly clocked-logic circuits. Ivan thinks we will see gradual acceptance and partial implementation of what he calls "islands of asynchrony" -- portions of circuits that take advantage of proven asynchronous logic. Prime candidates include the I/O parts of chips where system delays are uncertain, memory systems and arithmetic units. Related Links
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