'It's the Economy, Stupid'

Calculating the Cost of Energy, Area, and Delay in Circuit Design

By Al Riske

29.Jan.07-Jo Ebergen has a favorite quote. "It's the economy, stupid." He likes it because it neatly sums up his current concerns in circuit design.

A researcher in Sun Labs, Ebergen has been focused lately on the costs -- and trade-offs -- inherent in any design.

The key metrics: energy, area, and delay.

The key challenge: how to create the perfect balance between all three.

"First you have to know, does my circuit design waste any resources? Can I reduce my delay -- how long it takes to compute a certain result -- without giving up anything in terms of energy or area? Or can I reduce my energy without increasing any of my delay or area? Because, if I can do that, I should do it. That design is always better," says the Distinguished Engineer.

"You can even, perhaps, decrease delay, energy, and area all at the same time. But at a certain point you get to what is called a Pareto front, where you can no longer minimize all of your objectives. If you want to minimize one of them, you have to give up something in the others."

A 10-year Sun veteran with more than a dozen patents to his name, Ebergen juggles numerous research projects dealing with experimental hardware architectures and design aids. One of his top priorities right now, in fact, is creating a tool to help chip designers decide, very precisely, where they want to sit on the Pareto front.

"If you say, 'I absolutely have to reduce my delay here,' then it will cost you a little more in energy or area. And I would like to be able to characterize this trade-off as: This is the amount of energy or area that you'll have to pay for this improvement in delay, so the designer can decide, 'Okay, I'm willing to do that' or, 'Oh boy, I can't do it. The cost is too high for me,'" Ebergen says.

"Suppose you need to implement an adder. There are many different implementations consisting of many types of logic gates that come in many sizes. Basically a bigger gate can do more work in a shorter amount of time, but a bigger gate also consumes more energy and more area. So one of the problems a circuit designer faces is: 'How should I choose the sizes of all my gates so that this collection of gates will compute the result within the clock period and within my power and area budget?' That in itself is already quite a difficult task, because a circuit can comprise thousands of gates and trying to optimize such a circuit by hand is almost impossible."

The problem -- devising complex mathematical optimization routines to compute the trade-offs -- is one that Ebergen first tackled several years ago.

"I had tried to solve it and couldn't at the time," he says, "and there were other things in the group that were of higher priority."

In the meantime, things changed. While speed and size have always been critical factors in chip design, energy efficiency has become equally important, if not more so. And now new mathematical techniques are emerging.

"Some advances have been made recently in the area of convex optimization at a number of universities, and I'm trying to incorporate those advances into a CAD tool," Ebergen says.

"Last summer, I arranged some meetings with engineers from the Systems Group. I asked them a number of questions and told them what we were planning to do. They were very enthusiastic. So I thought, Let's do it. Let's see how far we get."

The ultimate goal of Ebergen's computer-aided design tool is to compute the various trade-off curves so that Sun's circuit designers can make informed choices.

"For a number of designs, the first thing designers try to do is to make sure their design fits within the timing constraints, but that may take them a number of days. They do not always succeed, and it may take a lot more effort before they've finally decided, 'Okay, I've made the right compromises here and there to fit within the clock period,' but to solve that problem using the minimum amount of energy or area as well -- that's an almost impossible task," Ebergen says. "This tool would simply compute the solution at the push of a button."

So if Ebergen succeeds, and early results have been positive, Sun could gain a substantial competitive edge.

"One of the big benefits will be to simplify the designer's task and thereby reduce the design time. Second, it will allow the designer to compare different designs and thereby pick the best one within his or her constraints. Thirdly, it may reduce the power consumption of the circuit," says the soft-spoken Dutchman.

"I have good connections with some of the circuit engineers so I asked, 'Okay, give me a small design to start with so that I can try out a small prototype because, first, I want to make sure my algorithm does the right thing, and, second, I want to see how efficient it is.' What we've already found out is, yes, it can improve the current design methods. For example, for the same delay you can reduce your energy. But we've also found that the convex optimization method that I'm currently using is not the fastest. I definitely hope to make some significant progress in the coming months by looking at more efficient optimization tools."

For quite some time, Ebergen says, he has been interested in the Theory of Logical Effort, developed by Sun Fellows Bob Sproull and Ivan Sutherland, which allows designers to draw conclusions about the cost of delay in any design, independent of the particular fabrication technology used to produce the chip.

"This is what gives the project an unconventional slant," Ebergen says. "Most of the papers I read from academia or industry do their cost analysis based on specific values for a particular fabrication technology."

Decoupling the design from the fabrication technology is important because it gives designers a way to make apples-to-apples comparisons.

"The trick is to normalize all your metrics to a particular standard inverter that you define. Often it's the smallest inverter you have. An inverter is a basic building block -- the most common one -- and once you define what your minimum size inverter is, then you can define what your unit of delay is, what your unit of energy is, and what your unit of area is in a particular technology. Then you normalize all your metrics according to those units. Now what you've done is you've hidden the technology-dependent values in your units. You can then compare the cost metrics of circuits that are built in completely different technologies."

In that regard, Ebergen is clearly indebted to Sproull and Sutherland (in fact, he joined Sun in order to work with Sutherland and they have collaborated on other projects, including radical designs such as computers without clocks), but he has made his own contributions here as well.

"I've tried to expand that theory," he says, "into reasoning about the other cost factors, energy and area."

Sutherland describes Ebergen as "the careful Dutchman."

"When Jo does it, it's done right," he says, "I admire Jo's ability to apply mathematics to practical problems to find useful answers."

Sproull, now director of Sun Labs, concurs.

"Sun is very fortunate to have Jo in Sun Labs. He thinks and works with the clarity of a theoretical mathematician, but he takes on practical problems that confront Sun engineers," Sproull says. "Ivan and I left the Theory of Logical Effort incomplete -- difficult to apply to a complete design or to embed in a CAD tool. Jo has made it whole, adding energy analysis, and has driven its practical use at Sun."