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Robert Drost
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Dr. Drost is a senior researcher in Sun
Microsystems
Laboratories. His research interests include high
speed clocking, data communication, 3-D chip
technologies, energy-efficient on-chip data communication and
computation,
and asynchronous timing of computer systems. |
Short Biography
Robert Drost received his B.S. and M.S. in Electrical Engineering in
1993 and Ph.D. degree in Electrical Engineering with a Ph.D. minor in
Computer Science in 2001, all from Stanford University.
Dr. Drost joined Sun Microsystems in 1993, worked on processor
projects, and since 1995 has been a member of the research staff at Sun
Microsystems Laboratories in Mountain View, California. He is the
Principal Investigator of communication circuit research
and his current research focuses on high bandwidth chip-to-chip
communication. This research encompasses high speed clocking, data
communication, and 3-D chip technologies with the goal to remove the
disparity between on-chip performance and off-chip data bandwidth. His
other areas of interest include energy-efficient on-chip data
communication and computation, and asynchronous timing of computer
systems. Dr. Drost received the Sun Microsystems Chairman's Award for
Innovation in 2004, and he holds 36 U.S. patents in the field of
electronic circuits.
Publications
- R. Drost, B. Wooley, “An 8-Gbps/pin Simultaneously
Bidirectional Transceiver in 0.35-micron CMOS,” IEEE Journal of
Solid-State Circuits, in press.
- R. Drost, R. D. Hopkins, R. Ho, I. Sutherland, “Proximity
Communication,” IEEE Journal of Solid-State Circuits, in press.
- R. Ho, J. Gainsley, R. Drost, “
Long
Wires and Asynchronous
Control,” IEEE Asynchronous Circuits and Systems Symposium, Apr.
2004.
- R. Drost, R. Ho, R. D. Hopkins, I. Sutherland, “Electronic
Alignment for Proximity Com-munication,” IEEE Int'l Solid-State
Circuits Conference, Feb. 2004.
- R. Drost, R. D. Hopkins, I. Sutherland, “ Proximity
Communications,” IEEE Custom Integrated Circuits Conference, pp.
469-472, Sept. 2003.
- H. Hatamkhani, K-L. J. Wong, R. Drost, C-K. K. Yang, “A
10-mW 3.6-Gbps I/O Transmitter,” IEEE VLSI Circuits Symposium, pp.
97-98, June 2003.
- W. Coates, R. Drost, “Congestion
and Starvation
Detection
in Ripple FIFOs,” IEEE Asynchronous Circuits and Systems Symposium,
pp.
36-45, May 2003.
- S. Bardwaj, S.S. Mohan, R. Drost, B.T. Khuri-Yakub, K.
Saraswat, “In-situ Film
Thickness and Temperature Monitoring Using a 2
GHz Acoustic Phase Measurement System,” IEEE Ultrasonics Symposium,
pp.
965-967, Dec. 1991.
Selected Articles
"New Sun Microsystems Chip May Unseat the Circuit Board," New York
Times, Sept. 22, 2003.
"Look Ma, No Wires," IEEE Spectrum, Nov. 12, 2003.
"An eye toward the future," Test and Measurement World, Nov 1, 2003.
"7 Hot Projects," MIT Technology Review, Dec. 2003/Jan. 2004.
Patents
Title
|
Issue Date
|
Number
|
| Bi-directional
Communication System |
18 May 2004 |
6,738,415
|
| Method
and Apparatus for Electrostatically Aligning Integrated Circuits |
23 March 2004 |
6,710,436
|
| Clock
Interpolation through Capacitive Weighting |
24 February 2004 |
6,696,876
|
| Long
Line Receiver for CMOS Integrated Circuits |
25 February 2003 |
6,526,552
|
| Selectable
Resistor and/or Driver for an Integrated Circuit with a Linear
Resistance |
21 January 2003 |
6,509,765
|
| Method
of Coupling and Aligning Semiconductor Devices Including Multi-Chip
Semiconductor Devices |
17 December 2002 |
6,495,396
|
| Method
and Apparatus that Models Neural Transmission to Amplify a
Capacitively-Coupled Input Signal |
29 October 2002 |
6,472,931
|
| Sense
Amplifier with Dual Linearly Weighted Inputs and Offset Voltage
Correction |
28 May 2002 |
6,396,308
|
| Techniques
for Making and Using an Improved Loop Filter which Maintains a Constant
Zero Frequency to Bandwidth Ratio |
16 April 2002 |
6,373,304
|
| Switched
Positive Feedback for Controlled Receiver Impedance |
7 May 2002 |
6,384,642
|
| Resistive
Arrayed High Speed Output Driver with Pre-Distortion |
11 December 2001 |
6,329,836
|
| Controlled
Impedance CMOS Receiver for Integrated Circuit Communication Between
Circuits |
6 November 2001 |
6,313,659
|
| Method
and Apparatus for Reducing Noise in Communication Channels having a
Shared Reference Signal |
16 October 2001 |
6,304,098
|
| Delay
Locking Using Multiple Control Signals |
27 February 2001 |
6,194,929
|
| Circuit
for Detecting and Decoding Phase Encoded Digital Serial Data |
14 November 2000 |
6,148,038
|
| Clock
Duty Cycle Control Technique |
4 July 2000 |
6,084,452
|
| Controlled
Phase Noise Generation Method for Enhanced Testability of Clock and
Data Generator and Recovery Circuits |
13 June 2000 |
6,076,175
|
| Adaptive
Equalization Technique Using Twice Sampled Non-Return to Zero Data |
25 April 2000 |
6,055,269
|
| Single
Rail Regulator |
29 February 2000 |
6,031,406
|
| Delay
Lock Loop with Transition Recycling for Clock Recovery of NRZ
Run-Length Encoded Serial Data Signals |
22 February 2000 |
6,028,903
|
| Frequency
Difference Detector for Use with an NRZ Signal |
1 February 2000 |
6,020,765
|
| Low
Phase Noise LC Oscillator for Microprocessor Clock Distribution |
18 January 2000 |
6,016,082
|
| Clock
Recovery System for High Speed Small Amplitude Data Stream |
9 November 1999 |
5,982,834
|
| Phase
Error Cancellation Method and Appartus for High Performance Data
Recovery |
5 October 1999 |
5,963,606
|
| On-Chip
Differential Resistance Technique with Noise Immunity and Symmetric
Resistance |
21 September 1999 |
5,955,911
|
| Time
to Charge Converter Circuit |
6 July 1999 |
5,920,215
|
| Dual
Differential Comparator with Weak Equalization and Narrow Metastability
Region |
15 June 1999 |
5,912,567
|
| CMOS
Integrated Circuit Regulator for Reducing Power Supply Noise |
18 May 1999 |
5,905,399
|
| Differential
High Speed Driver for Low Voltage Operation |
27 April 1999 |
5,898,297
|
| Active
Inductor Oscillator with Wide Frequency Range |
15 December 1998 |
5,850,163
|
| Phase
Detector for Clock Synchronization and Recovery |
25 August 1998 |
5,799,048
|
| CMOS
Current Controlled Delay Element Using Cascoded Complementary
Differential Amplifiers with Replicated Bias Clamp |
21 July 1998 |
5,783,953
|
| System
and Method for Serial to Parallel Data Conversion Using Delay Line |
7 July 1998 |
5,777,567
|
| Fully
Complementary Differential Output Driver for High Speed Digital
Communications |
16 June 1998 |
5,767,699
|
| ECL
to CMOS Converter |
16 January 1996 |
5,485,106
|
Interests
Training and competing in Triathlons
Cultivating Orchids
Travel
Aviation
Contact Information
Please direct Sun product and support questions
to the Online Support
Center.
Email:
robert.drost@sun.com
Phone:
office: 650 336 1169
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Postal address:
Sun Microsystems Research Laboratories
2600 Casey Avenue
Mailstop MTV29-001
Mountain View, CA 94043
USA
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