Dr. Wladek Olesinski Staff Engineer
Sedna Project
Sun Microsystems Laboratories
16 Network Circle umpk16-160 Menlo Park, CA 94025
Wladek (Wladyslaw) Olesinski is a researcher at Sun Microsystems Laboratories. He joined Sun in 2005. He has been working on scalable architectures and schedulers for large, high-speed switches in the Sedna project. Recently, he has also got interested in interconnects for Networks on Chips.
Previously, Wladek worked in laboratories at Alcatel and IBM as a researcher, network engineer and designer. His activities included research and design of congestion avoidance algorithms and traffic classification schemes. He was also involved in designing new protocols, including routing protocols for ad-hoc wireless networks, as well as in performance analysis and simulation of various networking devices.
He filed 13 patents and published over 25 papers.
Education:
* PhD 1999, University of Alberta, Edmonton, Canada
* MSc 1994, AGH University of Science and Technology, Krakow, Poland
Recent publications:
* D. Tsamis, B. Yolken, N. Bambos, W. Olesinski, H. Eberle, and N. Gura, "Backlog Aware Scheduling for Ingress Memories in High-Radix, Single-Stage Switches", To appear at IEEE GLOBECOM 2009, Honolulu, HI, Nov 30-Dec 4, 2009
* W. Olesinski, H. Eberle, N. Gura, B. Dickson, A. Silverton, S. Jarath, P. Yakutis, "Simple Fairness Protocols for Daisy Chain Interconnects", Symposium on High-Performance Interconnects (HotI'09), New York, Aug 26-27, 2009
* W. Olesinski, H. Eberle, N. Gura, "Scalable Alternatives to Virtual Output Queuing", To appear at International Conference on Communications (ICC'09), Dresden, Germany, June 14-18, 2009
* H. Eberle, P. J. Garcia, J. Flich, J. Duato, R. Drost, N. Gura, D. Hopkins, and W. Olesinski, "High-Radix Crossbar Switches Enabled by Proximity Communication", Best Paper Award at International Conference for High Performance Computing, Networking, Storage and Analysis (Supecomputing SC'08), Austin, TX, Nov 15-21, 2008
* A. Dua, B. Yolkien, N. Bambos, W. Olesinski, H. Eberle, and N. Gura, "Backlog Aware Scheduling for Large Buffered Crossbar Switches", International Conference on Communications (ICC'08), Bejing, China, May 19-23, 2008
* W. Olesinski, H. Eberle, and N. Gura, "Flow Control in Output Buffered Switch with Input Groups", High Performance Switching and Routing Conference (HPSR'08), Shanghai, China, May 15-17, 2008
* W. Olesinski, N. Gura, H. Eberle, and A. Mejia, "Low-Latency Scheduling in Large Switches", Symposium on Architectures for Networking and Communications Systems (ANCS'07), Orlando, Florida, Dec 3-4, 2007
* W. Olesinski, H. Eberle, and N. Gura, "OBIG: the Architecture of an Output Buffered Switch with Input Groups for Large Switches", IEEE GLOBECOM 2007, Washington, DC, Nov 26-30, 2007
* H. Eberle, A. Chow, B. Coates, J. Cunningham, R. Drost, J. Ebergen, S. Fairbanks, J. Gainsley, N. Gura, R. Ho, D. Hopkins, A. Krishnamoorthy, J. Lexau, W. Olesinski, J. Schauer, and T. Ono, "Multiterabit Switch Fabrics Enabled by Proximity Communication", Symposium on High-Performance Chips (Hot Chips), Stanford University, August 19-21, 2007
* A. Dua, N. Bambos, W. Olesinski, H. Eberle, and N. Gura, "Backlog Aware Low Complexity Schedulers for Input Queued Packet Switches", Symposium on High-Performance Interconnects (Hot Interconnects), Stanford University, August 22-24, 2007
* W. Olesinski, H. Eberle, and N. Gura, "PWWFA: Parallel Wave Front Arbiter for Large Switches", High Performance Switching and Routing Conference (HPSR'07), Brooklyn, New York, May 30-June 1, 2007
