Designing Fast Asynchronous Circuits

"Vanilla" Chip Vanilla: A chip designed to reveal details of asynchronous FIFO performance at very high throughput. Data gathered from this chip reveals behavior never before observed.

Dr. Ivan Sutherland's research project in asynchronous circuit design provides an excellent example of the foresight, passion, suspension of disbelief, luck, and courage he says are required for successful research.

Ten years ago, Ivan foresaw that the increasing complexity of integrated circuits threatened to slow the rate of performance improvement if changes in design were not made.

For more than 30 years, computer users have been the beneficiaries of "Moore's Law," a prediction that processor speed should double every 18 months. "My hope is that the asynchronous approach will keep processors on the Moore's Law curve in the years ahead," said Ivan. Without a shift to asynchronous design, Ivan believes, Moore's Law is not sustainable for more than few a generations of chips.

The asynchronous design project led by Ivan was an inaugural project of Sun Labs. The fundamental problem Ivan's team set out to solve was that as circuit complexity grows, circuit delay increases and inhibits system performance. With traditional synchronous chip design, the circuit's system clock, which regulates all chip operations, begins to create timing constraints that can limit the chip's performance. These constraints force engineers to specify clock speeds slower than the potential switching speed of transistors integrated into microprocessors. Today, logic transistors have the ability to run as much as 20 times faster than the system clocks that regulate them.

Islands of Asynchrony

The technology that Ivan's team has developed eliminates the system clock altogether--an absolutely heretical notion among traditional circuit designers. This approach, according to Ivan, will make it possible to design "islands of asynchronicity," portions of circuits that take advantage of asynchronous logic, in the near term--and, eventually, faster chips that consume less power as well as complete systems based on asynchronous technology.

The asynchronous design project is an example of how technological innovation occurs in the real world, according to Ivan. "If we knew how tough this was going to be in 1990 none of us would have persevered," he said. "But we kept going and we've learned a tremendous amount along the way. We've tried things that took us in the wrong direction but taught us indispensable lessons. We've developed technologies that didn't help us but will apply to many other projects. And we've had to reshape and refine our goals as we learned more."

"For example, early implementations based on our asynchronous technology were promising," he continued, "but they weren't fast enough. So we picked a different goal to seek: speed, Speed, SPEED! Everything we did centered around reducing complexity so performance could increase. And the result is that we've been very successful at increasing performance. We're absolutely confident the asynchronous approach will yield faster chips." Benchtop tests performed on a prototype asynchronous computer called FLEETzero demonstrate throughput of 1.2 billion data items per second, which is very fast for a device made using generic 0.35 micron CMOS IC process technology.

"Square FIFO" Chip "Fiendishly clever" idea by Jo Ebergen, the Square FIFO chip can provide maximum throughput over a wide range of occupancies. Its capacity grows with its area; its latency grows only with its perimeter.

After 10 years of hard work that resulted in a promising new technology, Ivan's team has arrived at only the first mile marker on the road to commercial development of asynchronous technology. "I fully believe that asynchronous chips will be designed and used in the years ahead," he said. "The camel's nose is under the tent. But will the camel follow? It becomes an economic issue now. To develop a viable product using our technology will require a substantial investment and several more developmental steps. And that's where corporate courage comes in. All we can do now is channel support to go to the next step."

"The asynchronous project demonstrates the research strategy of Sun Labs in action," said Jon Kannegaard, VP and Deputy Director of Sun Labs. "It's a risky project but one that could yield significant economic results. It's a project that requires collaboration and that benefits from our worldwide network of connections. It has the strength of leadership and engineering talent to propel it forward. And it's something that could make a dramatic impact on Sun, our customers, and our industry. That's what we're here for."

Related Links

• Asynchronous Design Group
• Asynchronous Design Group: Public Papers
• Asynchronous Technology: Beating the Clock

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