Designing Fast Asynchronous Circuits
Ivan E. Sutherland, Jon K. Lexau
Introduction by Ivan E. Sutherland
I often complained to the late Charlie Molnar about how hard our research project is. He always responded that I should be pleased with our opportunity to get "way ahead." Yes, it's been hard, but after a decade of research we've achieved exciting results. It is now easy to argue that, given a type of transistors, our circuits make them go as fast as they possibly can. This paper, one of four that we presented at the ASYNC 2001 conference, March 2001, in Salt Lake City, tells how we design our circuits; our other conference papers [see references below] describe some of our circuit forms, how to use them, and a novel computer design, called FLEET.
Our group in Sun Microsytems Laboratories works on circuits, called "asynchronous," that use internal timing instead of the more common external "clock." Instead of waiting for the next clock tick, our asynchronous circuits proceed as fast as they can, waiting only for data or for space to put results. Clocked circuits are more common in computers today because they are easier to design. Although asynchronous circuits are harder to design, we've been able to build and demonstrate an impressive collection of them. Our circuits are real; we build and test silicon chips to prove that they work.
To make fast circuits we put very little in them. For the past half decade we've been simplifying our circuits to make them faster. It is a remarkable fact of physics that any embellishment of a circuit must slow it down. The Theory of Logical Effort [book referenced below] relates hardware delay to logical complexity, showing how to compute the minimum delay for a given digital logic function. The paper you are about to read shows how we apply logical effort theory.
The paper describes a chip design process unlike any other. Most chip designs begin with a target speed. Instead, our process starts by making the promise that all logic gates will have a uniform but not yet specified delay. This promise simplifies the design task, but more importantly, it accommodates "lean and mean" logic circuits free of embellishment. The resulting circuits are very fast, not only because they are simple, but also because they use each transistor to its full potential.
Only at the end of the design process do we pick a value for the initially-unspecified delay. We make good on the initial promise of uniform delay by picking the widths of transistors so that every transistor drives a load proportional to its strength. Although the minimum achievable delay depends on the circuit details, it is also possible to lengthen the uniform delay to save power in a lower speed version. Because the choice of speed comes late in our design process, a single logic design can serve either high speed and low power applications by appropriate choice of transistor widths.
At the outset of this project we didn't anticipate finding a unique design process, but good research includes surprises. We set out to build a particular class of circuits, bringing some mathematical tools to bear on the problems we encountered. We built and tested real chips. We "listened to the silicon" to hear what its physics tells about what to design and how to design it. We tried many things that didn't work, learning from initial failures. From our effort has emerged the principal value of research, understanding. This paper, and the other papers and patents from Sun Labs, are attempts to share understanding with other people so that Sun, its engineers, its customers, and our society may benefit.
"Designing Fast Asynchronous Circuits." © 2001 Sun Microsystems, Inc. and IEEE. Reprinted, with permission, from Proceedings of the Seventh International Symposium on Advanced Research in Asynchronous Circuits and Systems, Salt Lake City, Utah, USA, 11-14 March 2001, pp. 184-93. Also © 2000, Sun Microsystems, Inc.
PUBLICATIONS:
- Ivan Sutherland, Bob Sproull and David Harris, "Logical Effort: Designing Fast CMOS Circuits," Morgan and Kaufmann Publishers, 1999. 1st Edition
REFERENCES:
- William Coates, Jon Lexau, Ian Jones, Scott Fairbanks and Ivan Sutherland, FLEETzero:
An Asynchronous Switching Experiment, Proceedings of the Seventh International Symposium on
Advanced Research in Asynchronous Circuits and Systems, Salt Lake City, Utah, USA, 11-14 March 2001.
pp. 173-182. (sml#2000-0768) Copyright 2001 by IEEE. Used by permission. Also Copyright 2000,
Sun Microsystems, Inc.
- Jo Ebergen, Squaring the FIFO in GasP, Proceedings of the Seventh International Symposium on
Advanced Research in Asychronous Circuits and Systems, Salt Lake City, Utah, USA, 11-14 March 2001.
pp. 194-205. (sml#2000-0755) Copyright 2001 by IEEE. Used by permission. Also Copyright 2000,
Sun Microsystems, Inc.
- Ivan Sutherland and Jon Lexau, Designing Fast Asynchronous Circuits, Proceedings of the Seventh
International Sumposium on Advanced Research in Asynchronous Circuits and Systems, Salt Lake city,
Utah, USA, 11-14 March 2001. pp. 184-193. (sml#2000-0759) Copyright 2001 by IEEE. Used by
permission. Also Copyright 2000,
Sun Microsystems, Inc. Slides. sml2001-0143.
- Ivan Sutherland and Scott Fairbanks, GasP: A Minimal FIFO Control, Proceedings of the Seventh
International Symposium on Advanced Research in Asynchronous Circuits and Systems, Salt Lake City,
Utah, USA, 11-14 March 2001. pp. 46-53. (sml#2000-0756) Copyright 2001 by IEEE. Used by
permission. Also Copyright 2000, Sun Microsystems, Inc.
- William Coates, Jo Ebergen, Jon Lexau, Scott Fairbanks, Ian Jones, Alex Ridgway,
David Harris and Ivan Sutherland A Counterflow Pipeline Experiment, Proceedings of the
Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems,
Barcelona, Spain. 19-21 April 1999. pp. 161-172. (sml#99-0068) Copyright 1999 by IEEE.
Used by permission.
- Charles Molnar, Ian Jones, William Coates and Jon Lexau, A FIFO Ring Performance Experiment,
Proceedings of the Third International Symposium on Advanced Research in Asynchronous Circuits and
Systems, Eindhoven, The Netherlands, 7-10 April 1997.
pp. 279-289. (sml#97-0015) Copyright 1997 by IEEE. Used by permission.
- Ivan Sutherland, Micropipelines: Turing Award, Communications of the ACM, June 1989. Vol 32, #6, pp. 720-738. sml#94:0412. Copyright 1989 by ACM, Inc. Used by permission. http://info.acm.org/pubs/toc/CRnotice.html