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In order to quickly decide which architectural features are to be included in future processors, we have developed a simulation approach that uses samples of benchmark program instruction traces. Rather than simulating a proposed architecture on the entire SPEC92 program suite of more than 100 billion instructions, we simulate using a set of samples of the SPEC92 suite containing less than 1% of the total instruction trace. Each of our samples contains a relatively short instruction trace that can be simulated quickly.
The technique described can be applied to existing architectural models to produce significant reductions in simulation time. Existing simulation tools can be leveraged to implement the trace sampling technique described.
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