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Fiscal 1994 Project Portfolio Report
Bob Sproull and Ivan Sutherland, Principal Investigators
bob.sproull@East.Sun.COM
ivan.sutherland@Eng.Sun.COM
Overall Objective
To explore the potential of the asynchronous design style. Asynchronous
systems may offer:
- Reduced design cost and time through re-use of designs
- Lower power consumption because no energy is consumed with unnecessary switching.
- An easy upgrade path to take advantage of technology improvements
because different parts may run at different speeds
- Good performance
Objective for FY94
To demonstrate the feasibility of building an asynchronous SPARC processor.
Description
We started FY94 with the basic architecture for the Sproull Pipeline Processor.
This has been the year to flesh out the basic idea into a real design.
One part of that work involves building and using an event driven simulator.
The simulator permits us to explore the effect on performance of changes in the
order and types of stages included in the pipeline.
A second part of our work has been the detailed design of the pipeline circuits. This activity is aimed not only at deciding exactly what to build, but more
importantly on making accurate estimates of performance. In order for the
simulator to produce meaningful answers we must have realistic estimates of
the delay of various parts of the design. Such estimates are realistic only when the circuit is known in detail and reasonable account is made for the geometry
of a proposed layout.
Accomplishments
During FY94 we mainly worked on understanding and improving the
performance of the processing pipeline. Our simulation reinforced our view
that the rate at which data moves through the pipeline is important. We have
therefore focused mainly on designs that move data through the pipeline as fast
as possible.
Our simulator has simulated the operation of many hundreds of millions of
instructions. So far its results must be interpreted carefully because we lack
accurate estimates of the basic delay numbers on which adequate estimates of
performance must be based. Nevertheless, the simulator has shown the value of
register scoreboards and cache improvements we have made to the architecture.
We now have a circuit plan that is as fast as we believe possible. We are busy
making detailed estimates of its performance. We have a tentative floor plan of
a proposed integrated circuit implementing our design.
References
Publications
"Counterflow Pipeline Processor Architecture," R. Sproull, I. Sutherland, C.
Molnar, to appear in the Fall 1994 issue of IEEE Design and Testing of Computers, SMLI TR-94-25.
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