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Lowered Supply and Threshold Voltage Effects on CMOS Circuit Characteristics
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Author(s):
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James Testa
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Report Number:
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Date Published:
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Available Formats:
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TR-1995-32
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June 1995
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Portable Document Format (PDF)
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| Abstract |
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Low Power Supply Voltages are currently being investigated in the attempt to lower power dissipation in CMOS ICs. Power dissipation becomes a major concern when both the number of transistors and the operating frequency increases. Lowering the powers supply voltage reduces the operating frequency by lowering MOSFET current. MOSFET current can be increased by lowering the threshold voltage, which increases the leakage current. This paper describes the operating limits of some static and dynamic CMOS circuits, as the power supply voltage is lowered and the threshold voltage is decreased and eventually becomes negative. The threshold voltage is theoretically determined where the frequency of operation is maximum for dynamic NOR gates with keeper MOSFETs, from the MOSFET current equations.
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