A Dissertation submitted to the Department of Electrical Engineering and
the Committee on Graduate Studies of Stanford University in partial
fulfillment of the requirements for the degree of Doctor of Philosophy.
Advances in integrated circuit technologies permit faster clocking speed
and increased logic density in chips. However, advances in chip packaging
technologies have not kept pace; hence the number of input/output pins and
input/output bandwidth per chip has increased less rapidly. The resulting
disparity creates the need for more bandwidth per pin. Single-ended
signalling and simultaneous bidirectional signalling methods may each
increase the bandwidth per pin by a factor of two. However, using these
signalling methods poses challenges in compensating for additional noise
sources and reduced noise rejection ratios.
This work presents the architecture, circuit techniques, and test results
for a single-ended simultaneously bidirectional interface capable of a
total throughput of 8 Gigabits per second per pin. The interface addresses
the noise reduction challenges by utilizing a pseudo-differential
reference with noise immunity approaching that of a fully differential
reference. Furthermore, noise generation is reduced by on-chip
termination, and low-skew near-end outgoing signal echo cancellation. A
test chip in a 0.35 micron digital CMOS technology uses these techniques
for an eight bit wide single-ended voltage-mode simultaneous bidirectional
interface and achieves a performance of 8 Gigabit per second per pin.
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