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Quantifying hardware counter sampling error in computer system workload characterization
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Author(s):
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Lodewijk Bonebakker
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Report Number:
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Date Published:
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Available Formats:
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TR-2007-163
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April 2007
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Portable Document Format (PDF)
Request Hard Copy
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| Abstract |
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This technical report explores workload characterization using processor hardware counter sampling. We assume that we are measuring a set of hardware counter events greater than the number of physical counters on the processor, i.e., the counters are set to measure different events after every measurement. We characterize workloads on typical time scales between 5 and 30 minutes, with different phasing properties.
We evaluate two competing strategies, a short sample time strategy designed to minimize overhead and a long sample time strategy designed to get better averaging. We find that both strategies are likely to produce accurate results, independent of underlying workload phasing, but neither strategy is ideal. We find that the optimal strategy is a fairly short sample time combined with continuous iteration over the counter set.
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